The present invention relates to the field of semiconductor processing, and more specifically to methods and apparatuses utilized in the formation of alignment marks during the fabrication of semiconductor devices.
In semiconductor integrated circuit (IC) fabrication processes, multiple layers of conductors and insulators are patterned and built one upon the other to construct the integrated circuit. During the fabrication process it is critical to align each subsequent layer to a previous layer with great precision in order to preserve circuit continuity. The degree of alignment precision is often a major factor which determines the manufacturability, yield, and profit of a process.
The alignment of one layer to the next is typically accomplished in a tool called a wafer stepper. The purpose of the stepper is to transfer a desired pattern situated on a reticle into a layer formed on the semiconductor wafer. The reticle typically contains a magnified version of the pattern to be generated. Generally, a semiconductor wafer, having an alignment mark, is coated with a transparent photosensitive material, referred to as photoresist. The wafer is then loaded into the wafer stepper tool. The stepper uses the alignment mark on the wafer as a reference point in adjusting the position of the reticle over the wafer to precisely align the reticle to the previous layer on the wafer.
Generally, a stepper utilizes a laser beam with a fixed wavelength to sense the position of the alignment mark on the wafer. The laser beam in the stepper is bounced off of the alignment mark on the semiconductor wafer surface to create a pattern of laser light. The diffraction from the alignment mark is reflected back to sensing devices in the stepper and is used as a signal to measure the exact position of the alignment mark. The quality of the defractive light from the alignment mark is a direct result of the structure of the alignment mark (i.e., a result of the materials and dimensions of the mark).
General problems associated with present techniques of generating alignment marks and aligning wafers are illustrated in FIGS. 1A–1G. As shown in FIG. 1A, individual integrated circuits 122 are generated in each stepping field of the stepper. Generally there are two blank stepping fields 120 which are skipped during alignment and exposure of the various reticles used to pattern the wafer. An alignment mark 102 is typically formed near the center of each blank stepping field 120. Alignment mark 102 is very small in relationship to the blank stepping field 120.
An alignment mark 102 is generally formed by etching a controlled depth into the semiconductor wafer 100, as shown in FIG. 1B. The etching step forms a step height 104 in the wafer 100. The step height 104 acts as the alignment mark. The step height 104, or depth, of alignment mark 102 is generally chosen to be some multiple, typically between ⅛ and ¼, of the wavelength of the laser light used by the stepper to conduct alignment. By utilizing an alignment mark at this multiple of the laser wavelength, the signal to noise ratio of the laser defraction is optimized, resulting in optimum alignment precision.
Next, as shown as FIG. 1C, isolation trenches 106 are formed in the wafer 100 and subsequent layers used to form the integrated circuit 122 are formed over the wafer 100. For example, etch-stop layer 107 and dielectric layer 108 are formed over the semiconductor wafer 100. Although the original alignment mark 102 is covered by subsequent layers, the step height and the therefore, the alignment mark 102, is replicated in the subsequently deposited layers. The replicated alignment marks are used for aligning and patterning the subsequent layers. That is, as more layers are added to the integrated circuit, the step height of the alignment mark 102 is propagated upward or is “built upward” with subsequent layers. The step height of the alignment mark 102 is therefore preserved in subsequent layers so that alignment of subsequent layers can be accomplished.
A problem with building up the alignment mark 102 is that it is incompatible with global planarization techniques, such as chemical-mechanical polishing. As more and more layers are added to the integrated circuit process, and circuit density increases, the requirement to planarize the integrated circuit topography at intermediate steps in the process becomes essential. It is important to planarize surfaces of multilevel integrated circuits because nonplanar surfaces interfere with the optical resolution of subsequent photolithography processing steps. This makes it extremely difficult to print high resolution lines. Additionally, nonplanar surface topographies can affect subsequently formed metal layers. If a step height is too large, there is a serious danger that open circuits will be formed in later metal layers. It has been found that the best way to planarize the integrated circuit topography is to planarize the dielectric layer 108 and to use a global planarization technique, such as chemical-mechanical polishing. Global planarization techniques planarize the entire wafer surface and make the surface essentially flat. Unfortunately, if the dielectric layer 108 is globally planarized, not only is the dielectric layer 108 over the integrated circuit area planarized, but so is the dielectric layer 108 over the alignment mark 102. The global planarization technique, therefore, removes the alignment mark 102 replicated in the dielectric layer 108, as shown in FIG. 1D.
The next step in the fabrication of integrated circuits typically is the formation of a gate layer 110. As shown in FIG. 1E, the gate layer 110 is formed over the dielectric layer 108. Although the alignment mark 102 has been removed during the global planarization step, the formation of the gate layer 110 and the next step, which is typically the formation of metal interconnects, can still proceed because a step caused by the alignment mark 102 is still visible through the transparent dielectric layer 108 and the gate layer 110. That is, the metal interconnects pattern can be aligned to the step height formed in the etch-stop layer 107.
The next step in the fabrication of integrated circuits typically is the formation of metal interconnects. As shown in FIG. 1E, a metallic layer 112 is formed over the gate layer 110 so that an electrical connection can be made. Because metallic layers are opaque, the step height of the alignment mark 102 formed in the etch-stop layer 107 is invisible to the stepper laser once the metallic layer 112 is formed. Without a visible alignment mark or an alignment mark replicated in metallic layer 112, it is impossible to align the reticle to perform subsequent steps.
One solution to the planarized alignment mark problem is an “open frame” process. In an open frame process, after contact alignment, a separate reticle is used to expose the area immediately surrounding alignment mark 102. Dielectric layer 108 over alignment mark 102 can then be etched away. Gate layer 110 and metal layer 112 can then be formed over an uncovered alignment mark 102 formed in the etch-stop layer 107, as shown in FIG. 1F. Alignment mark 102 replicated in metal layer 112 can then be used to align the reticle to generate of the metal interconnect pattern. Alternatively, the open frame process is carried out after gate and metal layer deposition. This process removes these layers from the alignment mark region.
The “open frame” solution works fine in processes that require only one global planarization step. Many integrated circuit processes, however, require two global planarization steps. When a second global planarization step is required, it is difficult to repeat the open frame alignment etch, due to the increased thickness of the dielectric material over the alignment mark. That is after the second global planarization, the depth of the dielectric material over the alignment mark is increased by the depth of the original open frame etch in comparison to the relevant structures on the integrated circuit.
Another solution to the planarized alignment mark problem, as shown in FIG. 1G, is to form a second completely independent alignment mark in the dielectric layer 108. In this process, after global planarization and contact formation, an exclusive masking and etching step is used to form a new alignment mark in the dielectric layer 108. This process requires considerable additional processing which adds no new value to the fabricated integrated circuit. This technique, therefore, is expensive. Also, there may be some misalignment between the two alignment marks.
Thus, what is required is a method of fabricating an alignment mark during multilayer semiconductor processes which is compatible with global planarization techniques, such as chemical-mechanical polishing (CMP) and which does not add additional cost or complexity to the fabrication process.